Device for supplying temperature dependent negative voltage

ABSTRACT

A negative voltage supply device includes a negative voltage detector and a negative voltage pumping unit. The negative voltage pumping unit pumps a negative voltage in response to a detection signal. The negative voltage detector detects a level of a negative voltage by using a first element and a second element, which are different in the degree of change in their respective resistance values depending on the temperature, and outputs the detection signal. The detection signal informs the negative voltage pumping unit that pumping of the negative voltage is no longer needed.

CROSS-REFERENCE TO RELATED APPLICATION

The present invention claims priority of Korean patent applicationnumber 10-2007-0020726, filed on Mar. 02, 2007, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The invention relates to a semiconductor device; and, more particularly,to a negative voltage supply device used for generating a negativevoltage lower than a ground voltage in a variety of semiconductordevices.

Hereinafter, a negative voltage supply device will be explained inconjunction with a memory device that employs the negative voltagesupply.

The reason that a memory device requires a negative voltage is to employa negative word line driving scheme. The negative word line drivingscheme is a scheme, in which, when a word line driver drives a wordline, it supplies a high voltage VPP to the word line for enablingthereof, while it supplies a negative voltage VBBW below a groundvoltage VSS to the word line for disabling thereof.

That is, the ground voltage VSS is usually supplied to the word line todisable the word line, but the negative voltage VBBW below the groundvoltage VSS is supplied thereto for the same purpose in the negativeword line driving scheme.

By using such a negative word line driving scheme, refreshcharacteristics as well as other AC parameters are improved. Especially,as the negative voltage VBBW below the ground voltage VSS is utilized asan electric potential to disable a word line, cell retention time isextended, resulting in an increase in a refresh cycle. Moreover, thenegative word line driving scheme is employed because it can decrease aVPP burden by the use of a low Vcc and improve a write recovery timeTWR.

FIG. 1 is a block diagram of a conventional negative voltage supplydevice.

As shown therein, the conventional negative voltage supply deviceincludes a negative voltage detector 10 for determining whether to pumpa negative voltage, and a negative voltage pumping unit having anoscillator 20, a pump controller 30, and a charge pump 40 for pumpingthe negative voltage.

The negative voltage detector 10 is a unit for detecting the level ofthe negative voltage VBBW, and outputs a detection signal bbweb fordetermining whether to pump the negative voltage. The oscillator 20receives the detection signal bbweb and outputs a periodic signal OSC.The pump controller 30 outputs pump control signals p1, p2, g1, and g2in response to the output signal OSC from the oscillator 20. Lastly, thecharge pump 40 pumps the negative voltage VBBW in response to the pumpcontrol signals p1, p2, g1, and g2. The negative voltage pumping unit20, 30 and 40 may be designed and implemented in various configurationsin a manner that it does not includes the pump controller 30 by allowingthe oscillator 20 to directly control the charge pump 40 as the case maybe.

That is, the negative voltage pumping unit 20, 30 and 40 stops thepumping operation when the level of the negative voltage VBBW detectedby the negative voltage detector 10 is sufficiently low (i.e., itsabsolute value is large). However, when the level of the negativevoltage VBBW detected by the negative voltage detector 10 is high (i.e.,its absolute value is small), the charge pump 40 performs the negativevoltage VBBW pumping operation.

FIG. 2 is a detailed circuit diagram of the negative voltage detector 10of FIG. 1.

As shown, a ground voltage VSS and a negative voltage VBBW are appliedto the gate of a transistor P01 and the gate of a transistor P02,respectively. The transistors P01 and P02 are operative in a linearregion, and function as a resistor, which distribute a high potentialVCORE and a low potential VSS. For instance, when the negative voltageVBBW is high (i.e., its absolute value is small) and thus resistance ofthe transistor P02 increases, an electric potential of DET nodeincreases, thereby outputting a detection signal bbweb as a ‘low’ signalbbweb from an inverter I03. On the contrary, when the negative voltageVBBW is low (i.e., its absolute value is large) and thus resistance ofthe transistor P02 decreases, an electric potential of DET node islowered, thereby outputting a detection signal bbweb as a ‘high’ signalbbweb from the inverter I03.

That is to say, the negative voltage detector 10 detects the level ofthe negative voltage VBBW by voltage distribution of the transistors P01and P02 taking the ground voltage VSS and the negative voltage VBBW,respectively.

FIG. 3 is a detailed circuit diagram of the oscillator 20 of FIG. 1.

As depicted in the drawing, the oscillator 20 may be configured in theshape of a ring oscillator composed of a NOR gate 21 accepting thedetection signal bbweb, and inverters I04 to I09.

When a ‘high’ sensing signal bbweb is inputted to the NOR gate 21, theNOR gate 21 always outputs a ‘low’ signal. However, when a ‘low’ sensingsignal bbweb is inputted, the NOR gate 21 serves as an inverter, so thata signal with a regular period is outputted by the inverters I04 to I09connected in a ring shape.

FIG. 4 is a detailed circuit diagram of the pump controller 30 of FIG.1, and FIG. 5 is an operation timing diagram of the pump controller 30.

As shown therein, the pump controller 30 is provided with NAND gates 31and 32 and a plurality of inverters I10 to I19, and outputs controlsignals p1, p2, g1, and g2 for control of the charge pump 40. Thecontrol signals p1 and p2 are signals for the charge pump 40 to pump,and the control signals g1 and g2 are sort of precharge signals.

FIG. 6 is a detailed circuit diagram of the charge pump 40 of FIG. 1.

The charge pump 40 functions to generate the negative voltage VBBW andis provided with PMOS transistors 41, 42, 43, and 44 which receive thecontrol signals p1, p2, g1, and g2 at nodes where its sources and drainsare connected, respectively, and operate as capacitors, as shown in FIG.6.

Briefly explaining the operation, the charge pump 40 pumps the negativevoltage VBBW upon receipt of the control signals p1 and p2, and makeselectric potentials at ‘a’ and ‘b’ nodes fall to the ground voltage VSSupon receipt of the control signals g1 and g2.

As described earlier, the memory device is provided with the negativevoltage supply device, which generates the negative voltage VBBW and isused as an electric potential for turning a cell transistor off, i.e., aword line disabling potential, thereby enabling negative word linedriving.

Meanwhile, leakage current of a cell transistor is characterized byincreasing as temperature rises. Thus, the value of the negative voltageVBBW at a high temperature needs to be decreased considerably, but doesnot need to do so if the temperature is lowered from room temperature toa lower temperature. Accordingly, using the prior art negative voltagesupply device which generates a fixed negative voltage VBBW regardlessof temperature causes an excessive current consumption in pumping thenegative voltage VBBW at room and low temperatures.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to provide anapparatus for supplying a negative voltage having various voltage leveldependent on voltage variation.

In accordance with an aspect of the present invention, there is provideda negative voltage supply device including a negative voltage detectorand a negative voltage pumping unit. The negative voltage pumping unitpumps a negative voltage in response to a detection signal. The negativevoltage detector detects a level of a negative voltage by using a firstelement and a second element, which are different in the degree ofchange in their respective resistance values depending on thetemperature, and outputs the detection signal. The detection signalinforms the negative voltage pumping unit that pumping of the negativevoltage is no longer needed.

In accordance with another aspect of the present invention, there isprovided a negative voltage supply device including a first negativevoltage detector, a second negative voltage detector, a third negativevoltage detector, a clamping part, and a negative voltage pumping unit.The first negative voltage detector detects a level of a negativevoltage to output a first detection signal indicating that the level ofthe negative voltage is less than a first voltage. The second negativevoltage detector detects a level of the negative voltage to provide asecond detection signal indicating that the level of the negativevoltage is less than a second voltage which is lower than the firstvoltage. The third negative voltage detector detects a level of thenegative voltage to generate a third detection signal indicating thatthe level of the negative voltage is less than a third voltage varyingwith temperature. The clamping part logically combines the firstdetection signal, the second detection signal, and the third detectionsignal to output a fourth detection signal causing a level of thenegative voltage to be dependent on temperature between the firstvoltage and the second voltage. The negative voltage pumping unit pumpsthe negative voltage in response to the fourth detection signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional negative voltage supplydevice.

FIG. 2 is a detailed circuit diagram of the negative voltage detectordepicted in FIG. 1.

FIG. 3 is a detailed circuit diagram of the oscillator depicted in FIG.1.

FIG. 4 is a detailed diagram of the pump controller shown in FIG. 1.

FIG. 5 is an operation timing diagram of the pump controller shown inFIG. 1.

FIG. 6 is a detailed circuit diagram of the charge pump of FIG. 1.

FIG. 7 is a detailed circuit diagram of a negative voltage detectorincluded in a negative voltage supply device in accordance with anembodiment of the present invention.

FIG. 8 is a block diagram of a negative voltage supply device inaccordance with another embodiment of the present invention.

FIGS. 9A, 9B, and 9C are detailed circuit diagrams of the first negativevoltage detector, the second negative voltage detector, and the thirdnegative voltage detector shown in FIG. 8, respectively.

FIG. 10 is a detailed circuit diagram of the clamping part shown in FIG.8.

FIG. 11 is a graph showing the relationship between levels of a negativevoltage generated by the negative voltage supply device shown in FIG. 8,and temperature.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the present invention will be setforth in detail with reference to the accompanying drawings so thatthose skilled in the art can easily carry out the invention.

A negative voltage supply device in accordance with an embodiment of theinvention includes a negative voltage detector that detects the level ofa negative voltage and outputs a temperature dependent signal, and anegative voltage pumping unit that pumps the negative voltage inresponse to the detection signal. That is, the negative voltage supplydevice of the invention has the same block diagram as that of theconventional negative voltage supply device shown in FIG. 1.

The negative voltage pumping unit for pumping a negative voltage can bethe same as shown in FIG. 6. As long as the negative voltage pumpingunit selectively pumps a negative voltage in response to a detectionsignal outputted from the negative voltage detector, it may beincorporated with the negative voltage detector of the presentinvention. Because it is required that the negative voltage pumping unitmeets the foregoing condition only and because the negative voltagepumping unit has been already explained earlier, a detailed descriptionthereof will be omitted here.

FIG. 7 is a detailed circuit diagram of a negative voltage detectorincluded in a negative voltage supply device in accordance with a firstembodiment of the present invention.

As shown in the drawing, the negative voltage detector of the negativevoltage supply device in accordance with the first embodiment of theinvention detects the level of a negative voltage by using a firstelement P02 and a second element N01, which are different in the degreeof change in their respective resistance values depending on thetemperature, and outputs a detection signal bbweb informing that pumpingof a negative voltage VBBW is no longer needed.

More specifically, the first element P02 operates as a pull-up resistorand the second element N01 operates as a pull-down resistor, and thedetection signal bbweb is generated by voltage distribution of the firstelement P02 and the second element N01. The first element P02 may beimplemented by a PMOS transistor P02 whose source receives a highvoltage VCORE and gate takes a ground voltage VSS. The second elementN01 may be implemented by an NMOS transistor N01 whose source receives anegative voltage VBBW and gate accepts the high voltage VCORE. The firstelement P02 and the second element N01 are connected in series, whereintheir drains are connected to each other.

The detection signal bbweb generated by the voltage distribution (inthis embodiment, voltage distribution between the high voltage VCORE andthe negative voltage VBBW) by the first element P02 and the secondelement N01 is outputted through at least one inverter I20, I21, or I22which takes the voltage of a connection part between the first elementP02 and the second element N01, i.e., the voltage of a drain terminalDET_T.

In the conventional negative voltage supply device, the same elements,e.g., PMOS transistors, were utilized as the first and second elementsfor the voltage distribution. Therefore, resistance change rates of thetwo elements were fixed depending on the temperature, and the negativevoltage VBBW levels at which a detection signal is outputted were fixedalthough the temperature was changed.

The present invention uses, as the first element P02 and the secondelement N01, a PMOS transistor P02 and an NMOS transistor N01 which havea different degree of change in their respective resistance valuesdepending on the temperature. That is, the two transistors P02 and N01exhibit different degrees of change in resistance value within theiroperating regions depending on the temperature, wherein, for example,properties of the PMOS transistor P02 are generally degraded faster thanthe NMOS transistor N01 at a low temperature. Thus, the level of thenegative voltage VBBW for enabling the detection signal bbweb may varydepending on temperature.

In operation, the PMOS transistor P02 has a fixed resistance value inturn-on state because its gate receives the ground voltage VSS. The NMOStransistor N01 also has a fixed resistance value in turn-on statebecause its gate takes the high voltage VCORE and its source accepts thenegative voltage VBBW. The more the level of the negative voltage VBBW(the greater the absolute value) being applied to the source of the NMOStransistor N01 is low, the more the Vgs value of the NMOS transistor N01becomes larger. This causes the NMOS transistor N01 to be turned on morestrongly, thereby lowering the electric potential of DET_T node, causingthe inverter I22 to output a ‘high’ detection signal bbweb, and thenegative voltage pumping unit to stop pumping the negative voltage VBBW.

As described above, in case of temperature variations, the PMOStransistor P02 and the NMOS transistor N01 have a different degree ofchange in their respective resistance values depending on thetemperature, so the electric potential of DET_T node is relativelyhigher at a higher temperatures than at lower temperatures. In otherwords, the level of the negative voltage VBBW at a high temperaturesneeds to be even lower than at room and lower temperatures to enable(‘high’) the detection signal bbweb. On the contrary, the detectionsignal bbweb can be enabled at lower temperatures although the level ofthe negative voltage VBBW at lower temperatures is relatively higherthan at a high temperature. Thus, when the negative voltage detector ofthe invention is used, it becomes possible to pump even lower negativevoltage VBBW (larger absolute value) at higher temperatures and to pumpeven higher negative voltage VBBW (smaller absolute value) at lowertemperatures.

For reference, the high voltage VCORE may be used as a bulk voltage ofthe PMOS transistor P02, and the negative voltage VBBW may be used as abulk voltage of the NMOS transistor N01. And, those two transistors P01and N01 may be set to have a certain size so that a switching level ofthe inverter I20 gets about ½VCORE.

Further, the application of VCORE as a high voltage in this embodimentis for illustrative purposes only, and various powers can be usedaccording to various designs. Preferably, the high voltage is a stablevoltage insensitive to temperature.

FIG. 8 is a block diagram of a negative voltage supply device inaccordance with a second embodiment of the invention.

As shown therein, the negative voltage supply in accordance with asecond embodiment of the invention includes a first negative voltagedetector 810, a second negative voltage detector 820, a third negativevoltage detector 830, a clamping part 840, and a negative voltagepumping unit 850.

Similar to the negative voltage supply device of the first embodimentdescribed earlier, the negative voltage supply device in accordance withthe second embodiment of the invention to be described with reference toFIGS. 8 to 10, supplies a negative voltage VBBW of a different leveldepending on temperature variations, but the voltage VBBW is restrictedwithin a maximum level and a minimum level. That is to say, the negativevoltage VBBW of too high a level or too low a level depending on thetemperature is prevented from being generated, which helps the negativevoltage supply device and a semiconductor device using the same tooperate very stably.

The first negative voltage detector 810 detects the level of thenegative voltage VBBW and outputs a first detection signal bbweb_1 thatis enabled when the negative voltage VBBW is less than a first voltage.That is, the first negative voltage detector 810 disables the firstdetection signal bbweb_1 if the negative voltage VBBW is higher than thefirst voltage that is the highest level of the negative voltage VBBW,and enables it otherwise.

The second negative voltage detector 820 detects the level of thenegative voltage VBBW and outputs a second detection signal bbweb_2 thatis enabled when the negative voltage VBBW is less than a second voltage.That is, the second negative voltage detector 820 disables the secondsignal bbweb_2 if the negative voltage VBBW is higher than the secondvoltage that is the lowest level of the negative voltage VBBW, andenables it otherwise.

The third negative voltage detector 830 detects the level of thenegative voltage VBBW and outputs a third detection signal bbweb_3indicating that the negative voltage VBBW level is not higher than atemperature-dependent third voltage. Namely, the negative voltage VBBWdetection level varies depending on the temperature. Therefore, thenegative voltage detector of FIG. 7 may be employed as it is.

The clamping part 840 logically combines the first detection signalbbweb_1, the second detection signal bbweb_2, and the third detectionsignal bbweb_3 to output a fourth detection signal bbweb_4 that causesthe negative voltage VBBW level to be temperature-dependent between thefirst voltage and the second voltage. More details on the clamping part840 will be provided later with reference to FIG. 10.

The negative voltage pumping unit 850 selectively pumps the negativevoltage VBBW in response to the fourth detection signal bbweb_4. Whilethe conventional negative voltage pumping unit pumps the negativevoltage VBBW in response to the detection signal bbweb, the negativevoltage pumping unit of FIG. 8 pumps the negative voltage VBBW inresponse to the fourth detection signal bbweb_4. Except for this, thenegative voltage pumping unit of this embodiment is the same as theconventional negative voltage pumping unit in terms of configuration andfunctions, so a detailed description thereof will be omitted here.

FIGS. 9A, 9B, and 9C are detailed circuit diagrams of the first negativevoltage detector 810, the second negative voltage detector 820, and thethird negative voltage detector 830 shown in FIG. 8, respectively.

Referring to the drawings, the first negative voltage detector 810 shownin FIG. 9A and the second negative voltage detector 820 shown in FIG. 9Bhave the same configuration as the conventional negative voltagedetector shown in FIG. 2, so their operating principles are identical toeach other.

However, the first negative voltage detector 810 shown in FIG. 9A hastransistors P03 and P04 whose sizes have been adjusted to enable thefirst detection signal bbweb_1 when the level of the negative voltageVBBW is lower than the first voltage (which is the highest voltage forlimiting the range of a negative voltage), and the second negativevoltage detector 820 shown in FIG. 9B has transistors P05 and P06 whosesizes have been adjusted to enable the second detection signal bbweb_2when the level of the negative voltage VBBW is lower than the secondvoltage (which is the lowest voltage for limiting the range of anegative voltage). That is, the detection levels are different from eachother.

The third negative voltage detector 830 shown in FIG. 9C is basicallythe same as the negative voltage detector shown in FIG. 7 in terms ofconfiguration and functions, except that its output signal is indicatedon the drawing as a third detection signal bbweb_3.

The operation of FIGS. 9A, 9B, and 9C has been described in theBackground of the Invention and in conjunction with FIG. 7, so it willbe omitted here.

FIG. 10 is a detailed circuit diagram of the clamping part 850 of FIG.8.

As mentioned earlier, the clamping part 850 logically combines thefirst, second, and third detection signals bbweb_1, bbweb_2, and bbweb_3to output a fourth detection signal bbweb_4 that causes the negativevoltage VBBW level to be temperature-dependent between the first voltageand the second voltage.

To be more specific, the fourth detection signal bbweb_4 has basicallythe same logic level as the third detection signal bbweb_3. However, thefourth detection signal bbweb_4 is disabled (the negative voltage ispumped) unconditionally when the first detection signal bbweb_1 isdisabled (when the negative voltage VBBW level is higher than the firstvoltage that is the maximum), and is enabled (the negative voltage isnot pumped) unconditionally when the second detection signal bbweb_2 isenabled (when the negative voltage VBBW level is lower than the secondvoltage that is the minimum).

As shown in the drawing, the clamping part 850 is provided with a firstNOR gate 1001 that logically combines the second detection signalbbweb_2 and the third detection signal bbweb_3, and a second NOR gate1002 that logically combines an inverted signal of the first detectionsignal bbweb_1 from an inverter I32 and an output of the first NOR gate1001 to output a fourth detection signal bbweb_4.

In operation, when the first detection signal bbweb_1 is disabled andinputted to the inverter I32 as a ‘low’ signal, a ‘high’ signal isapplied to the second NOR gate 1002. Then, the fourth detection signalbbweb_4 is disabled as a ‘low’ signal and outputted.

When the second detection signal bbweb_2 is enabled and becomes ‘high’,the first detection signal bbweb_1 is also enabled and becomes ‘high’(this is natural because the level of a negative voltage to enable thesecond detection signal is lower than the level of a negative voltage toenable the first detection signal). Therefore, the fourth detectionsignal bbweb_4 is enabled as ‘high’ and outputted from the second NORgate 1002.

In case the level of the negative voltage VBBW is between the firstvoltage and the second voltage, the first detection signal bbweb_1becomes ‘high’, while the second detection signal bbweb_2 becomes ‘low’.Thus, a logic level of the fourth detection signal bbweb_4 outputtedfrom the second NOR gate 1002 becomes equal to that of the thirddetection signal bbweb_3. At this time, the negative voltage VBBW, of alevel varying depending on the temperature, is pumped.

FIG. 11 is a graph showing the relation between levels of the negativevoltage VBBW generated by the negative voltage supply device of FIG. 8and temperature.

It shows that the first voltage level is set to −0.3 V, and the secondvoltage level is set to −0.8 V.

From the graph, it can be seen that the negative voltage supply devicegenerates the negative voltage VBBW of lower levels as temperatures areraised, but the maximum and minimum values thereof are limited to thefirst voltage (−0.3 V) and the second voltage (−0.8 V), respectively.

As explained so far, the negative voltage supply device of the inventioncan supply a low level negative voltage at high temperatures, and a highlevel negative voltage at low temperatures.

Thus, when the negative voltage supply device of the invention isapplied to a memory device, the leakage current of cell transistors canbe prevented by supplying a sufficiently low level negative voltage at ahigh temperature. In addition, unnecessary current consumption may beprevented by supplying, at a low temperature, a negative voltage ofhigher level than that of a high temperature.

In addition, when the negative voltage supply device of the invention isapplied to a system that requires a negative voltage and in which itslevel varies depending on temperature, current consumption of the entiresystem can be reduced.

Moreover, when implemented in the way as shown in FIG. 8, the negativevoltage supply of the invention supplies negative voltage of differentlevels according to temperature variations, while the maximum andminimum levels of the negative voltage to be supplied are restricted.This allows a system with the negative voltage supply device to operatevery stably.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A negative voltage supply device, comprising: a negative voltagepumping unit for pumping a negative voltage in response to a detectionsignal; and a negative voltage detector for detecting a level of anegative voltage by using a first element and a second element, whichare different in the degree of change in their respective resistancevalues depending on the temperature, and outputs said detection signal,wherein said detection signal informs the negative voltage pumping unitthat pumping of the negative voltage is no longer needed.
 2. Thenegative voltage supply device of claim 1, wherein the negative voltagedetector allows the level of the negative voltage to enable thedetection signal to be lowered as the temperature is raised.
 3. Thenegative voltage supply device of claim 1, wherein the negative voltagedetector allows the first element to operate as a pull-up resistor andthe second element to operate as a pull-down resistor, and generates thedetection signal by voltage distribution of the first element and thesecond element.
 4. The negative voltage supply device of claim 3,wherein the first element includes a PMOS transistor whose sourcereceives a high voltage and gate takes a ground voltage, the secondelement includes an NMOS transistor whose source receives the negativevoltage and gate accepts the high voltage, and the drains of the PMOStransistor and the NMOS transistor are connected to each other.
 5. Thenegative voltage supply device of claim 4, wherein the negative voltagedetector outputs the detection signal through at least one invertertaking a voltage of the drain terminal.
 6. The negative voltage supplydevice of claim 5, wherein the negative voltage pumping unit includes:an oscillator for generating a periodic signal in response to thedetection signal; a pump controller for outputting pump control signalsin response to an output signal from the oscillator; and a charge pumpfor pumping the negative voltage in response to the pump controlsignals.
 7. A negative voltage supply device, comprising: a firstnegative voltage detector for detecting a level of a negative voltage tooutput a first detection signal indicating that the level of thenegative voltage is less than a first voltage; a second negative voltagedetector for detecting a level of the negative voltage to provide asecond detection signal indicating that the level of the negativevoltage is less than a second voltage which is lower than the firstvoltage; a third negative voltage detector for detecting a level of thenegative voltage to generate a third detection signal indicating thatthe level of the negative voltage is less than a third voltage varyingwith temperature; a clamping part for logically combining the firstdetection signal, the second detection signal, and the third detectionsignal to output a fourth detection signal causing a level of thenegative voltage to be dependent on temperature between the firstvoltage and the second voltage; and a negative voltage pumping unit forpumping the negative voltage in response to the fourth detection signal.8. The negative voltage supply device of claim 7, wherein the thirdvoltage is lowered as the temperature is raised.
 9. The negative voltagesupply device of claim 7, wherein the third negative voltage detectordetects a level of the negative voltage by using a first element and asecond element, which have a different degree of change in theirrespective resistance values depending on temperature variations. 10.The negative voltage supply device of claim 9, wherein the thirdnegative voltage detector allows the first element to operate as apull-up resistor and the second element to operate as a pull-downresistor, and generates the third detection signal by voltagedistribution of the first element and the second element.
 11. Thenegative voltage supply device of claim 10, wherein the first elementincludes a PMOS transistor whose gate takes a ground voltage and sourcereceives a higher voltage, the second element includes an NMOStransistor whose source receives the negative voltage and gate acceptsthe higher voltage, and the drains of the PMOS transistor and the NMOStransistor are connected to each other.
 12. The negative voltage supplydevice of claim 11, wherein the third negative voltage detector outputsthe third detection signal through at least one inverter taking avoltage of the drain terminal.
 13. The negative voltage supply device ofclaim 7, wherein the clamping part causes the fourth detection signalhaving the same logic level as the third detection signal to be disabledwhen the first detection signal is disabled, and causes the fourthdetection signal to be enabled when the second detection signal isenabled.
 14. The negative voltage supply device of claim 13, wherein theclamping part includes: a first NOR gate for logically combining thesecond detection signal and the third detection signal; and a second NORgate for logically combining an inverted signal of the first detectionsignal and an output from the first NOR gate to output the fourthdetection signal.
 15. The negative voltage supply device of claim 14,wherein the negative voltage pumping unit includes: an oscillator forgenerating a periodic signal in response to the fourth detection signal;a pump controller for outputting pump control signals in response to anoutput signal from the oscillator; and a charge pump for pumping thenegative voltage in response to the pump control signals.